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Intel® oneAPI on Intel® FPGAs Development Flow Overview | oneAP | Intel Software

Intel® oneAPI on Intel® FPGAs Development Flow Overview | oneAP | Intel Software


Hi, I’m Alby, In this video,
I describe the various compilation stages and
developing designs with Data Parallel C++ on Intel FPGAs. The FPGA development
flow has three stages of compilation, emulation,
report generation, and hardware bitstream generation. First is the emulation stage. The emulation compilation
flow is typically done to verify the functional
correctness of the application. It will emulate the various
hardware functionalities and behaviors
available on the FPGA. The typical compilation
for emulation will only take a few
seconds using this command. And thus, your design
iterations can be done quickly to verify functionality. Note that emulation does not
emulate all feature sets that are available and does not
provide the actual performance expected on the hardware. Next is the report
generation stage, which can be done with
the following command. Typically, this is done
after the emulation stage to work out bottlenecks
in the design that will impact performance. Generating the HTML report
completes within minutes, but can vary based on
your design’s complexity. The outcome of this stage
is the “static HTML Reports” which will show you loop
bottlenecks, area utilization, and many other useful features. Keep in mind that
this command does not generate a hardware bitstream. You can watch the video that
covers optimizing for FPGAs with DP C++ in the links, as
well as read the optimization guide to learn how to use
the reports to improve your designs. Ideally, most of your time
developing your design should be spent iterating on
the first two stages, emulation and report generation. After you have met your area
and performance requirements, you can move on to the third
and final stage of compilation, hardware bitstream generation. In this stage, use this
command to generate the actual bitstream that will
be programmed onto the FPGA. This is the last
step before your code can be run on the FPGA. The process of
compiling for hardware takes a long time because
of the synthesis, placement, and routing processes. This is why we
recommend spending most of your time iterating
on the previous two stages. In this stage,
various optimizations will also be done to
generate high performing bitstreams customized for your
application and data flow. To recap, your design should
start with the emulation stage, which allows you to ensure
functional correctness and iterate quickly to
fix bugs in your design. When that’s
completed, the report should be generated to address
any area or performance bottlenecks in your design. Iterate on your design
and rerun the report until you’re satisfied
with the results. Finally, once the code
is functionally correct and performance is
optimized, a full bitstream can now be generated. If you follow these
stages, you will have a performance optimized
application for FPGAs. Make sure you check out
the resources in the links to learn more. Thanks for watching. [MUSIC PLAYING]

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